1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly, to an asynchronous static random access memory (SRAM) using a dynamic random access memory (DRAM) cell, and a method for driving the same.
2. Description of the Related Art
In general, a random access memory (RAM) of a semiconductor memory device is classified as either an SRAM or a DRAM. A unit memory cell for storing one-bit of information used in a conventional SRAM is implemented by four (4) transistors cross-coupled as a latch and two (2) transistors serving as a transfer gate.
In a general SRAM, since stored data is latched, a refresh operation for data retention is not required. Also, SRAMs typically are able to operate faster and consume less power than DRAMs.
However, since an SRAM unit memory cell is implemented by six (6) transistors, it occupies a larger die area than a DRAM unit memory cell implemented by one transistor and one capacitor. Therefore, the die area of an SRAM required for implementing a memory device with the same memory capacity is approximately 6 to 10 times that of a DRAM. So, the manufacturing cost is increased.
In order to reduce the cost, a conventional DRAM may be used instead of an SRAM. In this case, however, a DRAM controller is additionally required for periodic refresh operations. Also, the overall performance of the system itself may be deteriorated due to the periodic refresh operation and low-speed operation of the DRAM.
To overcome the disadvantages of the DRAM and SRAM, various implementations of the SRAM using DRAM cells continuously are being devised. One such implementation is disclosed in U.S. Pat. No. 5,999,474 to Wingyu Leung et al., in which a memory device consists of a multi-bank DRAM and an SRAM cache, so that the refresh of the memory can be hidden from the outside to be compatible with an SRAM.
However, according to the technology of the above-noted U.S. patent, an SRAM having the same storage capacity and configuration as a single DRAM bank, needs to be provided inside a memory device, and the circuit implementation is relatively complicated. Also, the memory device according to the above-noted U.S. patent is compatible with a synchronous SRAM in which external clocks are necessary. Thus, the technology based on the above-noted U.S. patent cannot be applied to a low power asynchronous SRAM for mobile equipment or the like.
To solve the above problems, it is an object of the invention to provide an asynchronous SRAM compatible memory device using a DRAM cell, which is easily implemented and can be used as a low power asynchronous SRAM.
Another object of the invention is to provide a method for driving the asynchronous SRAM compatible memory device.
Accordingly, to achieve the above object, there is provided an SRAM compatible memory device in which a leading address is primarily input and then a lagging address is secondarily input after a predetermined SRAM access time, the SRAM access time being elapsed for accessing valid data from the outside. The SRAM compatible memory device includes a DRAM memory array and a DRAM operation controller. The DRAM memory array has a plurality of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. The DRAM operation controller controls the DRAM memory array to perform an access operation after a predetermined DRAM access time (period) has elapsed from a time at which the leading address is primarily input. The SRAM access time (period) is equal to or longer than twice the DRAM access time.
According to another aspect of the invention, there is provided a SRAM compatible memory device including an array of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. A leading address is primarily input, and then a lagging address is secondarily input after a predetermined SRAM access time (period) has elapsed for accessing valid data from the outside. The SRAM access time is equal to or longer than the sum of a refresh time for refreshing the DRAM memory cells and a DRAM access time for effectively accessing the DRAM memory cells.
According to still another aspect of the invention, there is provided an SRAM compatible memory device. In the SRAM compatible memory device, a leading address is primarily input, and then a lagging address is secondarily input after a predetermined SRAM access time has elapsed for accessing valid data from the outside. The SRAM compatible memory device comprises a DRAM memory array and a DRAM operation controller. The DRAM memory array has a plurality of DRAM memory cells arranged in rows and columns. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. The DRAM operation controller controls the DRAM memory array to start an actual access operation during a predetermined DRAM access time (period), in response to the input of a leading address. The DRAM operation controller controls the DRAM memory array to input the lagging address after another DRAM access time from a time at which the actual operation is completed. The SRAM access time is equal to or longer than twice the DRAM access time.
To achieve another object of the invention, there is provided a method for driving an SRAM compatible memory device. The SRAM compatible memory device has a DRAM memory array including a plurality of DRAM memory cells arranged in a row and column type matrix. Each DRAM memory cell requires a refresh operation for retention of data stored within a predetermined refresh period. The method includes the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) allowing a predetermined DRAM access time to elapse after generation of the address transition detection signal, (d) after the step (c), performing an access operation to access the DRAM memory array for the duration of the DRAM access time, and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time measured from time of inputting the leading address. The SRAM access time is equal to or longer than twice the DRAM access time.
According to another aspect of the invention, there is provided a method for driving an SRAM compatible memory device. The SRAM compatible memory device includes an array of DRAM memory cells arranged in rows and columns, each DRAM memory cell requiring a refresh operation for retention of data stored within a predetermined refresh period. The method comprises the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) performing an access operation to access the DRAM memory array for the duration of a predetermined DRAM access time in response to the address transition detection signal, (d) allowing another DRAM access time to elapse after the step (c), and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time measured from the leading address input time. The SRAM access time is equal to or longer than twice the DRAM access time.
In the SRAM compatible memory device and method of driving the same according to the invention, the DRAM memory cell is operated twice within each access time, to be fully compatible with an asynchronous SRAM. Also, the SRAM compatible memory according to the invention can be easily implemented. Further, since the SRAM compatible memory according to the invention uses DRAM cells, it can function as a low power asynchronous SRAM.